1. Field of the Invention
This invention relates to integrated circuit (IC) manufacture technologies, and more particularly, to the architecture of a dual-chip IC package and a method of manufacturing the same, which can allow two chips to be mounted on the same leadframe in the same package for the provision of expanded functionality from one single IC package.
2. Description of Related Art
Integrated circuits are widely used in computers and intelligent electronic devices. Since IC chips are very small in size, they are usually supplied in packages for easy handling and utilization. The manufacture of ICs involves very complicated processes which can involve several hundreds of steps and needs several months to complete. The semiconductor industry is composed of four major branches: IC design, wafer fabrication, wafer testing, and packaging, each being a highly specialized field which requires stateof-the-art technologies and large amounts of capitals to accomplish.
The manufacture of an IC package includes three essential steps: preparing a wafer, forming a predesigned circuit on the wafer, and finally packing each die (chip) cutting apart from the wafer in a package. The packaging process is the final stage in the IC manufacture.
Conventional packaging methods, however, only allow the packing of one single chip in each package. In the case where it is desirable to provide various functions, such as memory and control logic, in the same IC package, these two functions must be formed in the same chip and then packed in a single-chip IC package in accordance with the conventional method. However, since the memory unit and the logic control unit, when implemented in integrated circuits, are different in layout specifications, such as line width, which would make the fabrication for such chips involve very complicated processes to achieve, resulting in a high manufacturing cost and low good yield rate.
FIGS. 1A-1C are schematic sectional diagrams used to depict the architecture of a conventional single-chip IC package and the steps involved in the method for manufacturing this 1C package.
Referring first to FIG. 1A, the 1C package is to be constructed on a leadframe 10 which is formed with two major parts: a die pad 13 in the center and a number of package pins 14 on the periphery of the die pad 13. In the packaging process, the first step is to perform a die-attach process so as to mount a chip 11 (which is a die cut apart from a fabricated wafer) on the front side of the die pad 13.
Referring next to FIG. 1B, in the subsequent step, a wire-bonding process is performed so as to connect the bonding pads (not shown) on the chip 11 respectively via a plurality of wires 15 to the corresponding ones of the package pins 14.
Referring further to FIG. 1C, in the subsequent step, a molding process is performed so as to form a molded compound 17 which hermetically encloses the chip 11, the die pad 13, and the wires 15 therein, with only the outer end of the package pins 14 being exposed to the outside.
The foregoing is a single-chip IC package which can enclose only one single chip therein. In the case where it is desirable to provide various functions from the same IC package, these functions must be formed in the same chip and then packaged in accordance with the method described above. However, as mentioned earlier, this would involve very complicated processes to achieve, resulting in a high manufacturing cost and low good yield rate.